Low Power Magnitude Comparator Circuit Design
نویسندگان
چکیده
منابع مشابه
Low Power Magnitude Comparator Circuit Design
This paper presents a new low power 2-Bit magnitude comparator using full adder technique. The proposed magnitude comparator (PTL logic) has been compared with existing magnitude comparator (GDI technique). The performance analysis of both magnitude comparators is done on basis of power consumption with respect to input voltage, temperature, and frequency; using Tanner EDA tool version 12.6 at ...
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Low power 8 bit GDI magnitude comparator is proposed in this paper which has an advantage of minimum power dissipation, reduced propagation delay and less number of transistors required as compare to conventional CMOS magnitude comparator. Proposed GDI magnitude comparator is designed at 100MHz frequency with 1.8 v supply voltage using 180nm technology using CADENCE VLSI EDA tools. The performa...
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In this Paper presents a new dynamic comparator is compared in terms of their voltage, speed and power. A new dynamic comparator which shows lower input offset voltage and high load drivability than the conventional dynamic comparators. This comparator not only achieves low offset but also exhibit high speed and low power in its operation, which can be used for low power high speed ADC applicat...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2014
ISSN: 0975-8887
DOI: 10.5120/16308-5535